Read e-book online Accelerating Test, Validation and Debug of High Speed Serial PDF

By Yongquan Fan

ISBN-10: 9048193974

ISBN-13: 9789048193974

High-Speed Serial Interface (HSSI) units became common in communications, from the embedded to high-performance computing structures, and from on-chip to a large haul. trying out of HSSIs has been a tough subject as a result of sign integrity concerns, lengthy attempt time and the necessity of pricey tools. Accelerating try, Validation and Debug of excessive velocity Serial Interfaces presents leading edge try out and debug ways and designated directions on tips on how to arrive to sensible try out of contemporary high-speed interfaces.

Accelerating attempt, Validation and Debug of excessive velocity Serial Interfaces first proposes a brand new set of rules that permits us to accomplish receiver try greater than a thousand instances quicker. Then an under-sampling dependent transmitter attempt scheme is gifted. The scheme can effectively extract the transmitter jitter and end the complete transmitter try out inside of 100ms, whereas the try out often takes seconds. The e-book additionally provides and exterior loopback-based trying out scheme, the place and FPGA-based BER tester and a singular jitter injection method are proposed. those schemes will be utilized to validate, try out and debug HSSIs with info cost as much as 12.5Gbps at a reduce attempt rate than natural ATE strategies. moreover, the publication introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, appropriate for comparing BER functionality lower than noise conditions.

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Extra resources for Accelerating Test, Validation and Debug of High Speed Serial Interfaces

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This includes the analysis across PVT corners. The traditional jitter tolerance test has always been very challenging. There are mainly two outstanding issues: the long test time, and the complexity to generate a controlled amount of jitter with a proper mix of different types of jitter [34]. The jitter tolerance test is notorious for its long test time. 1 Introduction 45 PJ Tolerance run 1013 bits to check the BER level. 5Gbps data rate, it takes 111 minutes (~2 hours) for the device to run so many bits.

Jitter tolerance is also the most important parameter in the receiver because of its direct link to the BER performance of the device. This chapter concentrates on accelerating the receiver jitter tolerance testing on ATE. The approaches developed in this chapter are design-independent, and they apply to HSSIs of any type. Non-ATE based testing techniques, such as design for test and loopbackbased testing, will be discussed later in Chapter 5. Jitter tolerance testing for HSSIs requires validating BER performance against the specifications prescribed by various standards at the 10-12 BER or lower.

P k q n−k k = 0 k! ) ) = ∑ p n (k ) = ∑ k =0 Then, the confidence level can be expressed as: CL = 1 − ∑ [ k =0 n! ( n − k )! 18 2 Background Fig. 2-5. Graph of the binomial distribution ( n = 10 8 , p = 10 −7 ) To qualify a BER p, we need to determine how many bits n must be transmitted with or few errors. We can first choose a hypothetical value of p and a desired CL, then solve the above CL equation to determine n and to prove the hypothesis. It is difficult to directly solve n and . One solution is to use Poisson theorem [31] to simplify solving n and .

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Accelerating Test, Validation and Debug of High Speed Serial Interfaces by Yongquan Fan


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